PIC18F2480/2580/4480/4580
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
24.10 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2 as necessary.
There are two mechanisms used for synchronization.
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
previous bit.
If the magnitude of the phase error is less than, or equal
to, the programmed value of the Synchronization Jump
Width, the effect of a resynchronization is the same as
that of a hard synchronization.
24.10.1 HARD SYNCHRONIZATION
If the magnitude of the phase error is larger than the
Synchronization Jump Width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the Synchronization Jump Width.
Hard synchronization is only done when there is a
recessive to dominant edge during a bus Idle condition,
indicating the start of a message. After hard synchroni-
zation, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge,
which has occurred to lie within the synchronization
segment of the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the Synchronization Jump Width.
24.10.3 SYNCHRONIZATION RULES
24.10.2 RESYNCHRONIZATION
• Only one synchronization within one bit time is
allowed.
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 24-6) or subtracted from Phase Segment 2 (see
Figure 24-7). The SJW is programmable between 1 TQ
and 4 TQ.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges fulfilling
rules 1 and 2 will be used for resynchronization,
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
DS39637D-page 342
© 2009 Microchip Technology Inc.
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