PIC18F2480/2580/4480/4580
REGISTER 24-49: MSEL1: MASK SELECT REGISTER 1(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
FIL7_1
FIL7_0
FIL6_1
FIL6_0
FIL5_1
FIL5_0
FIL4_1
FIL4_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL7_<1:0>: Filter 7 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL6_<1:0>: Filter 6 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL5_<1:0>: Filter 5 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL4_<1:0>: Filter 4 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
DS39637D-page 314
© 2009 Microchip Technology Inc.
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