PIC18F2480/2580/4480/4580
REGISTER 24-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-0
EXIDEN(1)
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>)
Unimplemented: Read as ‘0’
bit 3
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
EXIDEN: Extended Identifier Filter Enable Mask bit(1)
1= Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0= Both standard and extended identifier messages will be accepted
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Mask bits
Note 1: This bit is available in Mode 1 and 2 only.
REGISTER 24-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier Mask bits
REGISTER 24-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier Mask bits
DS39637D-page 310
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
