PIC18F2480/2580/4480/4580
REGISTER 24-50: MSEL2: MASK SELECT REGISTER 2(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIL11_1
FIL11_0
FIL10_1
FIL10_0
FIL9_1
FIL9_0
FIL8_1
FIL8_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL11_<1:0>: Filter 11 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL10_<1:0>: Filter 10 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL9_<1:0>: Filter 9 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL8_<1:0>: Filter 8 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
© 2009 Microchip Technology Inc.
DS39637D-page 315
MICROCHIP [ MICROCHIP ]
