PIC18F2480/2580/4480/4580
REGISTER 24-51: MSEL3: MASK SELECT REGISTER 3(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIL15_1
FIL15_0
FIL14_1
FIL14_0
FIL13_1
FIL13_0
FIL12_1
FIL12_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL15_<1:0>: Filter 15 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL14_<1:0>: Filter 14 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL13_<1:0>: Filter 13 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL12_<1:0>: Filter 12 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
DS39637D-page 316
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
