PIC18F2480/2580/4480/4580
REGISTER 24-48: MSEL0: MASK SELECT REGISTER 0(1)
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
FIL3_1
FIL3_0
FIL2_1
FIL2_0
FIL1_1
FIL1_0
FIL0_1
FIL0_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL3_<1:0>: Filter 3 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL2_<1:0>: Filter 2 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL1_<1:0>: Filter 1 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL0_<1:0>: Filter 0 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
© 2009 Microchip Technology Inc.
DS39637D-page 313
MICROCHIP [ MICROCHIP ]
