PIC18F2480/2580/4480/4580
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
11.5 PORTE, TRISE and LATE
Registers
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin. As
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
Depending on the particular PIC18F2480/2580/4480/
4580 device selected, PORTE is implemented in two
different ways.
For PIC18F4X80 devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and
RE2/CS/AN7/C2OUT) are individually configurable as
inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, these
pins will read as ‘0’s.
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
a
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
EXAMPLE 11-5:
INITIALIZING PORTE
CLRF
PORTE
LATE
0Ah
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
03h
; Value used to
; initialize data
; direction
; Turn off
; comparators
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Note:
On a Power-on Reset, RE<2:0> are
configured as analog inputs.
MOVLW
MOVWF
MOVWF
07h
CMCON
TRISC
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 11-1.
The Output Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
11.5.1
PORTE IN 28-PIN DEVICES
For PIC18F2X80 devices, PORTE is only available
when Master Clear functionality is disabled
(MCLRE = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
DS39637D-page 146
© 2009 Microchip Technology Inc.
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