PIC18F2480/2580/4480/4580
TABLE 11-7: PORTD I/O SUMMARY
Pin Name
Function
I/O
TRIS Buffer
Description
RD0/PSP0/
C1IN+
RD0
OUT
IN
0
1
x
x
1
DIG LATD<0> data output.
ST PORTD<0> data input.
PSP0
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
C1IN+
RD1
IN
ANA Comparator 1 Positive Input B. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD1/PSP1/
C1IN-
OUT
IN
0
1
x
DIG LATD<1> data output.
ST
PORTD<1> data input.
PSP1
OUT
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when
enabled).
IN
IN
x
1
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
C1IN-
RD2
ANA Comparator 1 negative input. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD2/PSP2/
C2IN+
OUT
IN
0
1
x
DIG LATD<2> data output.
ST
PORTD<2> data input.
PSP2
OUT
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when
enabled).
IN
IN
x
1
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
C2IN+
RD3
ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD3/PSP3/
C2IN-
OUT
IN
0
1
x
x
1
DIG LATD<3> data output.
ST
PORTD<3> data input.
PSP3
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
C2IN-
RD4
IN
ANA Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
RD4/PSP4/
ECCP1/P1A
OUT
IN
0
1
x
x
0
1
0
0
1
X
x
0
0
1
x
x
0
0
1
x
x
0
DIG LATD<4> data output.
ST
PORTD<4> data input.
PSP4
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
DIG ECCP1 compare output.
ECCP1
OUT
IN
ST
ECCP1 capture input.
P1A
RD5
OUT
OUT
IN
DIG ECCP1 Enhanced PWM output, Channel A.
DIG LATD<5> data output.
RD5/PSP5/
P1B
ST
PORTD<5> data input.
PSP5
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
DIG ECCP1 Enhanced PWM output, Channel B.
P1B
RD6
OUT
OUT
IN
RD6/PSP6/
P1C
DIG LATD<6> data output.
ST
PORTD<6> data input.
PSP6
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
DIG ECCP1 Enhanced PWM output, Channel C.
P1C
RD7
OUT
OUT
IN
RD7/PSP7/
P1D
DIG LATD<7> data output.
ST
PORTD<7> data input.
PSP7
P1D
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
DIG ECCP1 Enhanced PWM output, channel D.
OUT
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
DS39637D-page 144
© 2009 Microchip Technology Inc.
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