PIC18F2480/2580/4480/4580
TABLE 11-9: PORTE I/O SUMMARY
Pin Name
Function I/O TRIS Buffer
Description
RE0/RD/AN5
RE0
OUT
IN
0
1
1
1
DIG LATE<0> data output.
ST PORTE<0> data input.
TTL PSP read enable input.
RD
IN
AN5
IN
ANA A/D Input Channel 5. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/VPP/RE3
RE1
OUT
IN
0
1
1
1
DIG LATE<1> data output.
ST
PORTE<1> data input.
WR
IN
TTL PSP write enable input.
AN6
IN
ANA A/D Input Channel 6. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
C1OUT OUT
0
0
1
1
1
DIG Comparator 1 output.
DIG LATE<2> data output.
RE2
OUT
IN
ST
PORTE<2> data input.
CS
IN
TTL PSP chip select input.
AN7
IN
ANA A/D Input Channel 7. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
C2OUT OUT
0
x
x
1
DIG Comparator 2 output.
MCLR
VPP
IN
IN
IN
ST
ANA High-voltage detection; used by ICSP™ operation.
ST PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.
External Reset input. Disabled when MCLRE Configuration bit is ‘1’.
RE3
Legend:
PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTE(3)
LATE(2)
TRISE(3)
ADCON1
CMCON(3)
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2
RE1
RE0
58
58
58
56
57
LATE Output Latch Register
IBF
OBF
—
IBOV
VCFG1
C2INV
PSPMODE
VCFG0
C1INV
—
TRISE2
PCFG2
CM2
TRISE1
PCFG1
CM1
TRISE0
PCFG0
CM0
—
PCFG3
CIS
C2OUT
C1OUT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both PIC18F2X80 and PIC18F4X80 devices. All other bits are
implemented only when PORTE is implemented (i.e., PIC18F4X80 devices).
3: These registers are unimplemented on PIC18F2X80 devices.
DS39637D-page 148
© 2009 Microchip Technology Inc.
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