PIC18F2480/2580/4480/4580
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
11.4 PORTD, TRISD and LATD
Registers
buffers are TTL. See Section 11.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Note:
PORTD is only available on PIC18F4X80
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 11-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
The Output Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
TRISD
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Four of the PORTD pins are multiplexed with outputs
P1A, P1B, P1C and P1D of the Enhanced CCP
module. The operation of these additional PWM output
pins is covered in greater detail in Section 17.0
“Enhanced
Capture/Compare/PWM
(ECCP)
Module”.
Four of the PORTD pins are multiplexed with the input
pins of the comparators. The operation of these input
pins is covered in greater detail in Section 21.0
“Comparator Module”.
Note:
On a Power-on Reset, these pins are
configured as analog inputs.
© 2009 Microchip Technology Inc.
DS39637D-page 143
MICROCHIP [ MICROCHIP ]
