PIC18F2480/2580/4480/4580
FIGURE 11-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 11-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
(1)
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
58
58
58
58
58
58
55
58
58
58
56
57
(1)
LATD
LATD Output Latch Register
PORTD Data Direction Register
(1)
TRISD
(1)
PORTE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
RE0
(1)
LATE
LATE Output Latch Register
(1)
TRISE
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
TRISE2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PCFG2
CM2
TRISE1
INT0IF
TMR2IF
TMR2IE
TMR2IP
PCFG1
CM1
TRISE0
RBIF
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
SSPIF
SSPIE
SSPIP
PCFG3
CIS
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
TMR1IF
TMR1IE
TMR1IP
PCFG0
CM0
PIE1
TXIE
IPR1
RCIP
TXIP
ADCON1
VCFG1
C2INV
VCFG0
C1INV
(1)
CMCON
C2OUT
C1OUT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4X80 devices only.
DS39637D-page 150
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
