PIC18F2480/2580/4480/4580
TABLE 11-5: PORTC I/O SUMMARY
Pin Name
Function
I/O
TRIS
Buffer
Description
RC0/T1OSO/
T13CKI
RC0
OUT
IN
0
1
x
1
0
1
x
0
1
0
1
0
1
0
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
T13CKI
RC1
OUT
IN
ANA
ST
Timer1 oscillator output – overrides the TRIS<0> control when enabled.
Timer1/Timer3 clock input.
RC1/T1OSI
RC2/CCP1
OUT
IN
DIG
ST
LATC<1> data output.
PORTC<1> data input.
T1OSI
RC2
IN
ANA
DIG
ST
Timer1 oscillator input – overrides the TRIS<1> control when enabled.
LATC<2> data output.
OUT
IN
PORTC<2> data input.
CCP1
RC3
OUT
IN
DIG
ST
CCP1 compare output.
CCP1 capture input.
RC3/SCK/SCL
OUT
IN
DIG
ST
LATC<3> data output.
PORTC<3> data input.
SCK
OUT
DIG
SPI clock output (MSSP module) – must have TRIS set to ‘1’ to allow
MSSP module to control the bidirectional communication.
IN
1
0
ST
SPI clock input (MSSP module).
2
SCL
RC4
OUT
DIG
I C™/SM bus clock output (MSSP module) – must have TRIS set to ‘1’ to
allow MSSP module to control the bidirectional communication.
2
2
IN
OUT
IN
1
0
1
1
1
I C™/SMB I C/SM bus clock input.
RC4/SDI/SDA
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI
IN
ST
SPI data input (MSSP module).
2
SDA
OUT
DIG
I C/SM bus data output (MSSP module) – must have TRIS set to ‘1’ to
allow MSSP module to control the bidirectional communication.
2
2
IN
1
I C/SMB I C/SM bus data input (MSSP module) – must have TRIS set to ‘1’ to
allow MSSP module to control the bidirectional communication.
RC5/SDO
RC5
OUT
IN
0
1
0
0
1
0
1
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module).
LATC<6> data output.
PORTC<6> data input.
EUSART data output.
SDO
RC6
OUT
OUT
IN
DIG
DIG
ST
RC6/TX/CK
TX
CK
OUT
OUT
DIG
DIG
EUSART synchronous clock output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
IN
OUT
IN
1
0
1
1
1
ST
DIG
ST
EUSART synchronous clock input.
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
IN
ST
EUSART asynchronous data input.
OUT
DIG
EUSART synchronous data output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
IN
1
ST
EUSART synchronous data input.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
58
58
58
LATC
LATC Output Latch Register
TRISC
PORTC Data Direction Register
DS39637D-page 142
© 2009 Microchip Technology Inc.
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