PIC18F2480/2580/4480/4580
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
Mode 0
WAKIP
TXB2IP
RXB1IP
RXB0IP
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
FIFOWMIP
bit 0
Mode 1,2
WAKIP
TXBnIP
RXBnIP
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1)
1= High priority
0= Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1)
1= High priority
0= Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1= High priority
0= Low priority
bit 0
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1= High priority
0= Low priority
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
DS39637D-page 132
© 2009 Microchip Technology Inc.
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