PIC18F2480/2580/4480/4580
REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
CMIE(1)
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
R/W-0
R/W-0
ECCP1IE(2)
bit 0
OSCFIE
HLVDIE
TMR3IE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit(1)
1= Enabled
0= Disabled
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
ECCP1IE: CCP1 Interrupt Enable bit(2)
1= Enabled
0= Disabled
Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
2: This bit is available in PIC18F4X80 devices only.
DS39637D-page 128
© 2009 Microchip Technology Inc.