PIC18F2480/2580/4480/4580
REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CMIP(1)
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
R/W-1
R/W-1
ECCP1IP(2)
bit 0
OSCFIP
HLVDIP
TMR3IP
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit(1)
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
ECCP1IP: CCP1 Interrupt Priority bit(2)
1= High priority
0= Low priority
Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
2: This bit is available in PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 131
MICROCHIP [ MICROCHIP ]
