PIC18F2480/2580/4480/4580
REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
R/W-0
Mode 0
WAKIE
TXB2IE
RXB1IE
RXB0IE
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
RXBnIE FIFOWMIE(1)
R/W-0
Mode 1,2
WAKIE
TXBnIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1= Enable invalid message received interrupt
0= Disable invalid message received interrupt
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1= Enable bus activity wake-up interrupt
0= Disable bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1= Enable CAN bus error interrupt
0= Disable CAN bus error interrupt
When CAN is in Mode 0:
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1= Enable Transmit Buffer 2 interrupt
0= Disable Transmit Buffer 2 interrupt
When CAN is in Mode 1 or 2:
TXBnIE: CAN Transmit Buffer Interrupts Enable bit
1= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0
0= Disable all transmit buffer interrupts
bit 3
bit 2
bit 1
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)
1= Enable Transmit Buffer 1 interrupt
0= Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1)
1= Enable Transmit Buffer 0 interrupt
0= Disable Transmit Buffer 0 interrupt
When CAN is in Mode 0:
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1= Enable Receive Buffer 1 interrupt
0= Disable Receive Buffer 1 interrupt
When CAN is in Mode 1 or 2:
RXBnIE: CAN Receive Buffer Interrupts Enable bit
1= Enable receive buffer interrupt; individual interrupt is enabled by BIE0
0= Disable all receive buffer interrupts
bit 0
When CAN is in Mode 0:
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1= Enable Receive Buffer 0 interrupt
0= Disable Receive Buffer 0 interrupt
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIE: FIFO Watermark Interrupt Enable bit(1)
1= Enable FIFO watermark interrupt
0= Disable FIFO watermark interrupt
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
© 2009 Microchip Technology Inc.
DS39637D-page 129
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