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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
TABLE 11-1: PORTA I/O SUMMARY  
Pin Name  
Function  
I/O  
TRIS  
Buffer  
Description  
RA0/AN0/CVREF  
RA0  
OUT  
IN  
0
1
1
DIG  
TTL  
LATA<0> data output.  
PORTA<0> data input.  
AN0  
IN  
ANA A/D Input Channel 0. Enabled on POR; this analog input overrides the  
digital input (read as clear – low level).  
(1)  
CVREF  
OUT  
x
ANA Comparator voltage reference analog output. Enabling this analog  
output overrides the digital I/O (read as clear – low level).  
RA1/AN1  
RA1  
OUT  
IN  
0
1
1
DIG  
TTL  
LATA<1> data output.  
PORTA<1> data input.  
AN1  
RA2  
IN  
ANA A/D Input Channel 1. Enabled on POR; this analog input overrides the  
digital input (read as clear – low level).  
RA2/AN2/VREF-  
OUT  
IN  
0
1
1
DIG  
TTL  
LATA<2> data output.  
PORTA<2> data input.  
AN2  
IN  
ANA A/D Input Channel 2. Enabled on POR; this analog input overrides the  
digital input (read as clear – low level).  
VREF-  
RA3  
IN  
OUT  
IN  
1
0
1
1
ANA A/D and comparator negative voltage analog input.  
RA3/AN3/VREF+  
DIG  
TTL  
LATA<3> data output.  
PORTA<3> data input.  
AN3  
IN  
ANA A/D Input Channel 3. Enabled on POR; this analog input overrides the  
digital input (read as clear – low level).  
VREF+  
RA4  
IN  
OUT  
IN  
1
0
1
1
0
1
1
ANA A/D and comparator positive voltage analog input.  
RA4/T0CKI  
DIG  
TTL  
ST  
LATA<4> data output.  
PORTA<4> data input.  
Timer0 clock input.  
T0CKI  
RA5  
IN  
RA5/AN4/SS/HLVDIN  
OUT  
IN  
DIG  
TTL  
LATA<5> data output.  
PORTA<5> data input.  
AN4  
IN  
ANA A/D Input Channel 4. Enabled on POR; this analog input overrides the  
digital input (read as clear – low level).  
SS  
IN  
IN  
1
1
x
TTL  
Slave select input for MSSP.  
HLVDIN  
OSC2  
ANA High/Low-Voltage Detect external trip point input.  
OSC2/CLKO/RA6  
OSC1/CLKI/RA7  
OUT  
ANA Output connection; selected by FOSC<3:0> Configuration bits.  
Enabling OSC2 overrides digital I/O.  
CLKO  
RA6  
OUT  
x
DIG  
Output connection; selected by FOSC<3:0> Configuration bits.  
Enabling CLKO overrides digital I/O (FOSC/4).  
OUT  
IN  
0
1
x
DIG  
TTL  
LATA<6> data output.  
PORTA<6> data input.  
OSC1  
CLKI  
RA7  
IN  
ANA Main oscillator input connection determined by FOSC<3:0>  
Configuration bits. Enabling OSC1 overrides digital I/O.  
IN  
x
ANA Main clock input connection determined by FOSC<3:0>  
Configuration bits. Enabling CLKI overrides digital I/O.  
OUT  
IN  
0
1
DIG  
TTL  
LATA<7> data output.  
PORTA<7> data input.  
Legend:  
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input  
Note 1: Available on 40/44-pin devices only.  
DS39637D-page 136  
© 2009 Microchip Technology Inc.  
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