PIC18F2450/4450
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F2450/4450)
Value on
POR, BOR on page
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
00-0 0000 49, 55
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
--00 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
xxxx xxxx 49, 83
xxxx xxxx 49, 83
0000 000x 49, 87
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
—
—
bit 21(1)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
INTCON3
INDF0
RBPU
INTEDG0
INT1IP
INTEDG1
—
INTEDG2
INT2IE
—
TMR0IP
—
—
RBIP
1111 -1-1 49, 88
11-0 0-00 49, 89
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
49, 68
49, 69
49, 69
49, 69
49, 69
POSTINC0
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000 49, 68
xxxx xxxx 49, 68
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
xxxx xxxx
N/A
49,
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
49, 68
49, 69
49, 69
49, 69
49, 69
POSTINC1
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000 49, 68
xxxx xxxx 49, 68
---- 0000 49, 59
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
50, 68
50, 69
50, 69
50, 69
50, 69
POSTINC2
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000 50, 68
xxxx xxxx 50, 68
---x xxxx 50, 66
0000 0000 50, 113
xxxx xxxx 50, 113
1111 1111 50, 111
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
3:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
5:
6:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 63
MICROCHIP [ MICROCHIP ]
