PIC18F2450/4450
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
5.3.5
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend
downward to occupy the top segment of Bank 15, from
F60h to FFFh. A list of these registers is given in
Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
(1)
FFFh
FFEh
FFDh
TOSU
TOSH
TOSL
FDFh
INDF2
FBFh
FBEh
CCPR1H
CCPR1L
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
IPR1
PIR1
PIE1
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
(1)
(1)
FDEh POSTINC2
FDDh POSTDEC2
FBDh CCP1CON
(1)
(2)
(2)
FFCh
FFBh
FFAh
FF9h
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
FBCh
FBBh
FBAh
FB9h
—
—
—
—
—
(1)
(2)
(2)
(2)
(2)
FDBh PLUSW2
—
(2)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FSR2H
FSR2L
—
(2)
—
(2)
FF8h TBLPTRU
FF7h TBLPTRH
STATUS
TMR0H
TMR0L
T0CON
FB8h BAUDCON
—
(2)
(2)
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(3)
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TBLPTRL
TABLAT
PRODH
PRODL
TRISE
TRISD
(3)
(2)
—
TRISC
TRISB
TRISA
OSCCON
INTCON
INTCON2
INTCON3
FD2h HLVDCON
FD1h WDTCON
(2)
—
(2)
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
RCON
TMR1H
TMR1L
T1CON
TMR2
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
—
(1)
(2)
INDF0
—
(1)
(1)
(2)
FEEh POSTINC0
—
(3)
FEDh POSTDEC0
LATE
(1)
(3)
FECh PREINC0
LATD
(1)
FEBh PLUSW0
PR2
RCSTA
LATC
LATB
LATA
(2)
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
—
UEIR
(2)
(2)
—
—
UIE
(2)
(2)
(2)
—
—
—
UIR
(1)
(2)
(1)
(2)
INDF1
—
FA7h EECON2
—
UFRMH
UFRML
(1)
(1)
(2)
(2)
FE6h POSTINC1
—
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EECON1
—
(2)
(2)
(2)
(2)
(2)
(2)
FE5h POSTDEC1
—
—
—
—
—
—
(1)
(2)
FE4h PREINC1
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTE
—
(1)
(3)
(2)
FE3h PLUSW1
F83h PORTD
—
(2)
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
F82h
F81h
F80h
PORTC
PORTB
PORTA
—
(2)
—
(2)
—
Note 1: Not a physical register.
2: Unimplemented registers are read as ‘0’.
3: These registers are implemented only on 40/44-pin devices.
DS39760A-page 62
Advance Information
© 2006 Microchip Technology Inc.
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