PIC18F2450/4450
5.3.2
BANK SELECT REGISTER (BSR)
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is
accomplished with a RAM banking scheme. This
divides the memory space into 16 contiguous banks of
256 bytes. Depending on the instruction, each location
can be addressed directly by its full 12-bit address, or
an 8-bit low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. PIC18F2450/
4450 devices implement three complete banks, for a
total of 768 bytes. Figure 5-5 shows the data memory
organization for the devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The eight bits in the instruction show the loca-
tion in the bank and can be thought of as an offset from
the bank’s lower boundary. The relationship between
the BSR’s value and the bank division in data memory
is shown in Figure 5-6.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-6 indicates which banks are implemented.
BSR. Section 5.3.3 “Access Bank” provides
detailed description of the Access RAM.
a
5.3.1
USB RAM
Bank 4 of the data memory is actually mapped to
special dual port RAM. When the USB module is
disabled, the GPRs in these banks are used like any
other GPR in the data memory space.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
When the USB module is enabled, the memory in this
bank is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use this area of USB RAM
that is not allocated as USB buffers for normal scratch-
pad memory or other variable storage. In practice, the
dynamic nature of buffer allocation makes this risky at
best. Bank 4 is also used for USB buffer management
when the module is enabled and should not be used for
any other purposes during that time.
Additional information on USB RAM and buffer
operation is provided in Section 14.0 “Universal
Serial Bus (USB)”.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 59
MICROCHIP [ MICROCHIP ]
