PIC18F2450/4450
TABLE 5-2:
File Name
REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Value on
POR, BOR on page
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
IDLEN
—
—
IRVST
—
—
HLVDEN
—
OSTS
HLVDL3
—
—
HLVDL2
—
SCS1
HLVDL1
—
SCS0
HLVDL0
SWDTEN
BOR
0--- q-00 50, 31
0-00 0101 50, 183
HLVDCON
WDTCON
RCON
VDIRMAG
—
—
—
--- ---0
50, 202
IPEN
SBOREN(2)
—
RI
TO
PD
POR
0q-1 11q0 50, 42
xxxx xxxx 50, 119
xxxx xxxx 50, 119
0000 0000 50, 115
0000 0000 50, 122
1111 1111 50, 122
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
T2CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
BAUDCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR2
—
T2CKPS0 -000 0000 50, 121
xxxx xxxx 50, 182
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx 50, 182
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
--00 0000 50, 173
--00 qqqq 50, 174
0-00 0000 50, 175
xxxx xxxx 50, 124
xxxx xxxx 50, 124
--00 0000 50, 123,
01-0 0-00 51, 156,
0000 0000 50, 157
0000 0000 50, 157
0000 0000 50, 164
0000 0000 50, 162
0000 0010 51, 154
0000 000x 51, 155
0000 0000 51, 74
-x-0 x00- 51, 75
1-1- -1-- 51, 95
0-0- -0-- 51, 91
0-0- -0-- 51, 93
-111 -111 51, 94
-000 -000 51, 90
-000 -000 51, 92
---- -111 51, 110
1111 1111 51, 108
11-- -111 51, 106
1111 1111 51, 103
-111 1111 51, 100
---- -xxx 51, 110
xxxx xxxx 51, 108
xx-- -xxx 51, 106
xxxx xxxx 51, 103
-xxx xxxx 51, 100
---- x000 51, 109
xxxx xxxx 51, 108
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
—
DC1B0
SCKP
CCP1M3
BRG16
CCP1M2
—
CCP1M1
WUE
CCP1M0
ABDEN
ABDOVF
RCIDL
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
Data Memory Control Register 2 (not a physical register)
—
OSCFIP
OSCFIF
OSCFIE
—
CFGS
—
—
USBIP
USBIF
USBIE
RCIP
RCIF
RCIE
—
FREE
—
WRERR
—
WREN
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
LATE2
LATD2
LATC2
LATB2
LATA2
WR
—
—
—
PIR2
—
—
—
—
—
PIE2
—
—
—
—
—
IPR1
ADIP
ADIF
ADIE
—
TXIP
TXIF
TXIE
—
—
TMR2IP
TMR2IF
TMR2IE
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATE1
LATD1
LATC1
LATB1
LATA1
RE1(3)
RD1
TMR1IP
TMR1IF
TMR1IE
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATE0
LATD0
LATC0
LATB0
LATA0
RE0(3)
RD0
PIR1
—
—
PIE1
—
—
TRISE(3)
TRISD(3)
TRISC
—
—
TRISD7
TRISC7
TRISB7
—
TRISD6
TRISC6
TRISB6
TRISA6(4)
—
TRISD5
—
TRISD4
—
TRISD3
—
TRISB
TRISB5
TRISA5
—
TRISB4
TRISA4
—
TRISB3
TRISA3
—
TRISA
LATE(3)
LATD(3)
LATC
—
LATD7
LATC7
LATB7
—
LATD6
LATC6
LATB6
LATA6(4)
—
LATD5
—
LATD4
—
LATD3
—
LATB
LATB5
LATA5
—
LATB4
LATA4
—
LATB3
LATA3
RE3(5)
RD3
LATA
PORTE
PORTD(3)
—
RE2(3)
RD7
RD6
RD5
RD4
RD2
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
3:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
5:
6:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
DS39760A-page 64
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
