PIC18F2450/4450
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
00-0 0000
-000 0000
-0x0 000-
-xxx xxx-
0--0 0000
0--0 0000
-000 0000
-000 0000
---- -xxx
xxxx xxxx
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
00-0 0000
-000 0000
-0x0 000-
-xxx xxx-
0--0 0000
0--0 0000
-000 0000
-000 0000
---- -xxx
xxxx xxxx
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
uu-u uuuu
-uuu uuuu
-uuu uuu-
-uuu uuu-
u--u uuuu
u--u uuuu
-uuu uuuu
-uuu uuuu
---- -uuu
uuuu uuuu
UEIR
UIE
UIR
UFRMH
UFRML
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
DS39760A-page 52
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
