PIC18F2450/4450
FIGURE 21-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 21-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
31
Watchdog Timer Time-out Period
(no postscaler)
—
4.00
TBD
ms
32
33
34
TOST
Oscillator Start-up Timer Period
1024 TOSC
—
65.5
2
1024 TOSC
TBD
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
—
—
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs VDD ≤ BVDD (see D005)
μs
TIRVST Time for Internal Reference
Voltage to become Stable
20
50
37
38
39
TLVD
TCSD
Low-Voltage Detect Pulse Width
CPU Start-up Time
200
5
—
—
1
—
10
—
μs
μs
ms
VDD ≤ VLVD
TIOBST Time for INTRC to Stabilize
—
Legend: TBD = To Be Determined
DS39760A-page 286
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
