PIC18F2450/4450
TABLE 21-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TosH2ckL OSC1 ↑ to CLKO ↓
TosH2ckH OSC1 ↑ to CLKO ↑
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
—
12
13
14
15
16
17
18
18A
TckR
TckF
CLKO Rise Time
CLKO Fall Time
—
—
TckL2ioV CLKO ↓ to Port Out Valid
TioV2ckH Port In Valid before CLKO ↑
TckH2ioI Port In Hold after CLKO ↑
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns (Note 1)
0.25 TCY + 25
—
—
ns (Note 1)
ns (Note 1)
ns
0
—
150
—
TosH2ioI OSC1 ↑ (Q2 cycle) to
Port Input Invalid
PIC18FXXXX
100
200
ns
PIC18LFXXXX
—
ns VDD = 2.0V
(I/O in hold time)
19
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
20
TioR
Port Output Rise Time
Port Output Fall Time
INT Pin High or Low Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
ns
20A
21
—
ns VDD = 2.0V
TioF
—
ns
21A
22†
23†
—
ns VDD = 2.0V
TINP
TCY
TCY
ns
ns
TRBP
RB7:RB4 Change INT High or Low Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 21-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 21-4 for load conditions.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 285
MICROCHIP [ MICROCHIP ]
