PIC18F2450/4450
FIGURE 21-11:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 21-4 for load conditions.
122
TABLE 21-13: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXXXX
—
—
—
—
—
—
40
100
20
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
121
122
Tckrf
Tdtrf
Clock Out Rise Time and Fall Time PIC18FXXXX
(Master mode)
PIC18LFXXXX
50
ns VDD = 2.0V
ns
Data Out Rise Time and Fall Time
PIC18FXXXX
20
PIC18LFXXXX
50
ns VDD = 2.0V
FIGURE 21-12:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK ↓ (DT hold time)
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 289
MICROCHIP [ MICROCHIP ]
