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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
For the module to issue an address Acknowledge, it is  
sufficient to match only on addresses that do not have an  
active address mask.  
16.4.3.2  
Address Masking  
Masking an address bit causes that bit to become a  
“don’t care”. When one address bit is masked, two  
addresses will be Acknowledged and cause an  
interrupt. It is possible to mask more than one address  
bit at a time, which makes it possible to Acknowledge  
up to 31 addresses in 7-Bit Addressing mode and up to  
63 addresses in 10-Bit Addressing mode (see  
Example 16-2).  
The I2C Slave behaves the same way, whether  
address masking is used or not. However, when  
address masking is used, the I2C slave can  
Acknowledge multiple addresses and cause interrupts.  
When this occurs, it is necessary to determine which  
address caused the interrupt by checking SSPxBUF.  
In 10-Bit Addressing mode, ADMSK<5:2> bits mask  
the corresponding address bits in the SSPxADD regis-  
ter. In addition, ADMSK1 simultaneously masks the two  
LSbs of the address (SSPxADD<1:0>). For any  
ADMSK bits that are active (ADMSK<n> = 1), the cor-  
responding address bit is ignored (SSPxADD<n> = x).  
Also note that although in 10-Bit Addressing mode, the  
upper address bits reuse part of the SSPxADD register  
bits, the address mask bits do not interact with those  
bits. They only affect the lower address bits.  
Note 1: ADMSK1 masks the two Least Significant  
bits of the address.  
In 7-Bit Addressing mode, Address Mask bits,  
2: The two Most Significant bits of the  
address are not affected by address  
masking.  
ADMSK<5:1>  
(SSPxCON2<5:1>),  
mask  
the  
corresponding address bits in the SSPxADD register. For  
any ADMSK bits that are set (ADMSK<n> = 1), the cor-  
responding address bit is ignored (SSPxADD<n> = x).  
EXAMPLE 16-2:  
7-Bit Addressing:  
ADDRESS MASKING EXAMPLES  
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)  
ADMSK<5:1> = 00111  
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh  
10-Bit Addressing:  
SSPxADD<7:0>= A0h (10100000) (the two MSbs of the address are ignored in this example, since they are  
not affected by masking)  
ADMSK<5:1> = 00111  
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh  
© 2009 Microchip Technology Inc.  
DS39682E-page 165  
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