PIC18FXX20
FIGURE 26-11:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note:
Refer to Figure 26-6 for load conditions.
FIGURE 26-12:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage stable
36
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
30
31
TmcL
TWDT
MCLR Pulse Width (low)
Watchdog Timer Time-out Period (No
Postscaler)
2
7
—
18
—
33
µs
ms
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power up Timer Period
I/O high impedance from MCLR Low
or Watchdog Timer Reset
1024 TOSC
—
72
2
1024 TOSC
—
ms
µs
TOSC = OSC1 period
28
—
132
—
35
36
TBOR
TIVRST
Brown-out Reset Pulse Width
Time for Internal Reference
Voltage to become stable
200
—
—
20
—
50
µs
µs
VDD ≤ BVDD (see D005)
VDD ≤ VLVD
37
TLVD
Low Voltage Detect Pulse Width
200
—
—
µs
DS39609A-page 326
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
