PIC18FXX20
FIGURE 26-9:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
Data from External
Address
AD<15:0>
163
162
150
151
160
155
161
166
167
168
169
ALE
CE
164
171
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address out valid to ALE ↓ (address
0.25 TCY – 10
—
—
—
ns
setup time)
151
TalL2adl ALE ↓ to address out invalid (address hold
5
—
ns
time)
155
160
161
162
163
164
165
166
167
168
169
171
171A
TalL2oeL ALE ↓ to OE ↓
TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
ToeH2adD OE ↑ to AD driven
TadV2oeH LS Data valid before OE ↑ (data setup time)
ToeH2adl OE ↑ to data in invalid (data hold time)
TalH2alL ALE pulse width
10
0
0.125 TCY
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
0.125 TCY – 5
20
0
—
—
TCY
0.5 TCY
0.25 TCY
—
ToeL2oeH OE pulse width
TalH2alH ALE ↑ to ALE ↑ (cycle time)
0.5 TCY – 5
—
0.75 TCY – 25
Tacc
Address valid to data valid
—
0.5 TCY – 25
0.625 TCY + 10
—
Toe
OE ↓ to data valid
—
—
—
—
TalL2oeH ALE ↓ to OE ↑
TalH2csL Chip Enable active to ALE ↓
TubL2oeH AD valid to Chip Enable active
0.625 TCY – 10
0.25 TCY – 20
—
10
DS39609A-page 324
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
