PIC18FXX20
FIGURE 26-10:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
166
Data
Address
Address
AD<15:0>
153
150
151
156
ALE
CE
171
171A
154
WRH or
WRL
157A
157
UB or
LB
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address out valid to ALE ↓ (address setup time)
TalL2adl ALE ↓ to address out invalid (address hold time)
TwrH2adl WRn ↑ to data out invalid (data hold time)
0.25 TCY – 10
—
—
—
—
—
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
151
153
154
156
157
157A
166
171
171A
5
5
TwrL
WRn pulse width
0.5 TCY – 5
0.5 TCY – 10
0.25 TCY
0.125 TCY – 5
—
0.5 TCY
—
—
—
0.25 TCY
—
TadV2wrH Data valid before WRn ↑ (data setup time)
TbsV2wrL Byte select valid before WRn ↓ (byte select setup time)
TwrH2bsI WRn ↑ to byte select invalid (byte select hold time)
TalH2alH ALE ↑ to ALE ↑ (cycle time)
TalH2csL Chip Enable active to ALE ↓
TubL2oeH AD valid to Chip Enable active
0.25 TCY – 20
—
—
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 325
MICROCHIP [ MICROCHIP ]
