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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
26.4.3  
TIMING DIAGRAMS AND SPECIFICATIONS  
FIGURE 26-7:  
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)  
Q4  
Q1  
Q2  
Q3  
Q4  
Q1  
OSC1  
CLKO  
1
4
3
4
3
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS  
Param. No. Symbol  
Characteristic  
Min  
Max  
Units  
Conditions  
(1)  
1A  
FOSC  
External CLKI Frequency  
DC  
DC  
DC  
0.1  
4
4
4
5
25  
40  
4
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
kHz  
EC, ECIO, PIC18FX620/X720  
EC, ECIO, PIC18FX520  
RC osc  
XT osc  
HS osc  
HS + PLL osc, PIC18FX520  
HS + PLL osc, PIC18FX620/X720  
LP Osc mode  
(1)  
Oscillator Frequency  
4
25  
10  
6.25  
200  
(1)  
EC, ECIO, PIC18FX620/X720  
1
TOSC  
External CLKI Period  
25  
ns  
ns  
EC, ECIO, PIC18FX520  
160  
(1)  
Oscillator Period  
250  
250  
10,000  
ns  
ns  
RC osc  
XT osc  
25  
100  
100  
250  
250  
160  
ns  
ns  
ns  
HS osc  
HS + PLL osc, PIC18FX520  
HS + PLL osc, PIC18FX620/X720  
25  
µs  
LP osc  
(1)  
2
3
TCY  
TosL,  
TosH  
Instruction Cycle Time  
100  
30  
2.5  
10  
ns  
ns  
µs  
ns  
ns  
ns  
ns  
TCY = 4/FOSC  
XT osc  
LP osc  
HS osc  
XT osc  
LP osc  
External Clock in (OSC1)  
High or Low Time  
4
TosR,  
TosF  
External Clock in (OSC1) Rise  
or Fall Time  
20  
50  
7.5  
HS osc  
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations except PLL. All  
specified values are based on characterization data for that particular oscillator type under standard operating conditions  
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or  
higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied  
to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.  
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)  
Param. No. Sym  
Characteristic  
Min  
Typ†  
Max  
Units  
Conditions  
FOSC  
Oscillator Frequency Range  
4
10  
MHz HS mode  
FSYS  
On-chip VCO System Frequency  
PLL Start-up Time (Lock Time)  
CLKO Stability (Jitter)  
16  
-2  
40  
2
+2  
MHz HS mode  
ms  
%
t
rc  
CLK  
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not  
tested.  
DS39609A-page 322  
Advance Information  
2003 Microchip Technology Inc.  
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