PIC18FXX20
FIGURE 26-15:
PARALLEL SLAVE PORT TIMING (PIC18F8X20)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 26-6 for load conditions.
TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data in valid before WR ↑ or CS ↑
20
25
—
—
ns
ns
(setup time)
Extended Temp. range
63
64
TwrH2dtI
WR ↑ or CS ↑ to data–in
PIC18FXX20
PIC18LFXX20
20
35
—
—
—
—
80
90
ns
ns
ns
ns
invalid (hold time)
TrdL2dtV RD ↓ and CS ↓ to data–out valid
Extended Temp. range
65
66
TrdH2dtI
TibfINH
RD ↑ or CS ↓ to data–out invalid
Inhibit of the IBF flag bit being cleared from
WR ↑ or CS ↑
10
—
30
3 TCY
ns
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 329
MICROCHIP [ MICROCHIP ]
