PIC18CXX2
FIGURE 8-12: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
POR, BOR
Value on all
other resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port data latch when written; port pins when read
LATD Data Output Bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
0000 000x 0000 000u
TRISD
PORTE
LATE
PORTD Data Direction Bits
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
LATE Data Output Bits
PORTE Data Direction Bits
TMR0IF INT0IF RBIF
TRISE
INTCON
IBF
OBF
IBOV
TMR0IF
PSPMODE
INT0IE
—
GIE/
GIEH
PEIE/
GIEL
RBIE
PIR1
PSPIF
PSPIE
PSPIP
ADFM
ADIF
ADIE
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF
SSPIE
SSPIP
PCFG3
CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
ADIP
ADCON1
ADCS2
PCFG2
PCFG1
PCFG0
--0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’.
Shaded cells are not used by the Parallel Slave Port.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 91
MICROCHIP [ MICROCHIP ]
