PIC18CXX2
TABLE 4-2:
REGISTER FILE SUMMARY (Cont.’d)
Value on
all other
resets
Value on
POR,
BOR
Filename
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(note 3)
OSCCON
LVDCON
WDTCON
RCON
—
—
—
—
—
—
—
SCS
---- ---0
--00 0101
---- ---0
0q-1 11qq
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
---- ---0
--00 0101
---- ---0
0q-q qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
—
—
—
—
IRVST
—
LVDEN
—
LVDL3
—
LVDL2
—
LVDL1
—
LVDL0
SWDTE
BOR
IPEN
LWRT
—
RI
TO
PD
POR
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T2CKPS0
Timer2 Register
PR2
Timer2 Period Register
TOUTPS3
T2CON
SSPBUF
SSPADD
—
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
SSP Receive Buffer/Transmit Register
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
TMR3H
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 00-0
00-- 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
WCOL
GCEN
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
ACKEN
SSPM3
RCEN
SSPM2
PEN
SSPM1
RSEN
SSPM0
SEN
A/D Result Register High Byte
A/D Result Register Low Byte
ADCS1
ADFM
ADCS0
ADCS2
CHS2
—
CHS1
—
CHS0
GO/DONE
PCFG2
—
ADON
PCFG3
PCFG1
PCFG0
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
T3CCP1
CCP1M2
CCP2M2
T3SYNC
CCP1M1
CCP2M1
TMR3CS
CCP1M0
CCP2M0
TMR3ON
Capture/Compare/PWM Register2 High Byte
Capture/Compare/PWM Register2 Low Byte
—
—
DC2B1
DC2B0
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
SPBRG
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
RCREG
TXREG
TXSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
RCSTA
ADDEN
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read ’0’ in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 45
MICROCHIP [ MICROCHIP ]
