PIC18CXX2
FIGURE 21-11: PARALLEL SLAVE PORT TIMING (PIC18C4X2)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data in valid before WR↑ or CS↑
20
25
—
—
ns
ns
(setup time)
Extended Temp range
63
64
TwrH2dtI
TrdL2dtV
WR↑ or CS↑ to data–in invalid PIC18CXXX
20
35
—
—
ns
ns
(hold time)
PIC18LCXXX
RD↓ and CS↓ to data–out valid
—
—
80
90
ns
ns
Extended Temp range
65
66
TrdH2dtI
TibfINH
RD↑ or CS↓ to data–out invalid
10
—
30
ns
Inhibit of the IBF flag bit being cleared from
3TCY
WR↑ or CS↑
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 259
MICROCHIP [ MICROCHIP ]
