PIC18CXX2
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
Operands:
[ label ] BSF f,b,a
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a
[0,1]
Operation:
1 → f<b>
None
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Decode
Read
register ’f’
Process
Data
Write
register ’f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG=
0x0A
0x8A
Before Instruction
After Instruction
PC
=
=
address (HERE)
address (Jump)
FLAG_REG=
After Instruction
PC
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 203
MICROCHIP [ MICROCHIP ]
