PIC18CXX2
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
Operands:
[ label ] BCF f,b,a
Syntax:
Operands:
Operation:
n
0 ≤ f ≤ 255
0 ≤ b ≤ 7
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
a
[0,1]
Operation:
0 → f<b>
None
Status Affected:
Encoding:
None
Status Affected:
Encoding:
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ’1’, then the
program will branch.
Description:
Bit 'b' in register 'f' is cleared. If ’a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
BCF
FLAG_REG, 7, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG = 0xC7
If No Jump:
Q1
After Instruction
Q2
Q3
Q4
FLAG_REG = 0x47
Decode
Read literal
’n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative=
PC
If Negative=
PC
1;
=
address (Jump)
0;
=
address (HERE+2)
DS39026B-page 200
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
