PIC18CXX2
CLRF
Clear f
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
[label] CLRF f,a
0 ≤ f ≤ 255
Operands:
Operation:
a
[0,1]
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ = 1, then the bank will
be selected as per the BSR value
(default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
Write
register ’f’
CLRWDT
Example:
CLRF
=
FLAG_REG,1
Example:
Before Instruction
WDT counter
=
=
?
Before Instruction
FLAG_REG
0x5A
0x00
After Instruction
WDT counter
WDT Postscaler =
TO
PD
0x00
After Instruction
0
1
1
FLAG_REG
=
=
=
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 207
MICROCHIP [ MICROCHIP ]
