PIC18CXX2
BC
Branch if Carry
[ label ] BC
ANDWF
AND WREG with f
[ label ] ANDWF f,d,a
0 ≤ f ≤ 255
Syntax:
Operands:
Operation:
n
Syntax:
-128 ≤ n ≤ 127
Operands:
d
a
[0,1]
[0,1]
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
Status Affected:
Encoding:
None
(WREG) .AND. (f) → dest
1110
0010
nnnn
nnnn
Status Affected:
Encoding:
N,Z
Description:
If the Carry bit is ’1’, then the pro-
gram will branch.
0001
01da
ffff
ffff
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
BSR will not be overridden
(default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
1
Q Cycle Activity:
If Jump:
Q Cycle Activity:
Q1
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
’n’
Process
Data
Write to PC
Decode
Read
register ’f’
Process
Data
Write to
destination
No
No
No
No
operation
operation
operation
operation
If No Jump:
Q1
ANDWF
REG, 0, 0
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read literal
’n’
Process
Data
No
WREG
REG
=
=
0x17
0xC2
operation
After Instruction
HERE
BC
5
Example:
WREG
REG
=
=
0x02
0xC2
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
=
=
=
1;
PC
address (HERE+12)
0;
If Carry
PC
address (HERE+2)
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 199
MICROCHIP [ MICROCHIP ]
