PIC18CXX2
TABLE 19-2: PIC18CXXX INSTRUCTION SET (Cont.’d)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn
1110 0110 nnnn
1110 0011 nnnn
1110 0111 nnnn
1110 0101 nnnn
1110 0001 nnnn
1110 0100 nnnn
1101 0nnn nnnn
1110 0000 nnnn
1110 110s kkkk
1111 kkkk kkkk
0000 0000 0000
0000 0000 0000
1110 1111 kkkk
1111 kkkk kkkk
0000 0000 0000
1111 xxxx xxxx
0000 0000 0000
0000 0000 0000
1101 1nnn nnnn
0000 0000 1111
0000 0000 0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
0100 TO, PD
0111 C
kkkk None
kkkk
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address1st word
2nd word
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
1
1
1
1
2
1
2
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into standby mode
2
2
1
0000 1100 kkkk
0000 0000 0001
0000 0000 0000
kkkk None
001s None
0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven
low by an external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instruction will be executed as a NOP, unless
the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program
memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 195
MICROCHIP [ MICROCHIP ]
