PIC18F6525/6621/8525/8621
TABLE 1-2:
PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X
PIC18F8X2X
(6)
PORTH is a bidirectional I/O port
Digital I/O.
.
RH0/A16
RH0
—
79
I/O
O
ST
TTL
A16
External memory address 16.
RH1/A17
RH1
—
—
—
—
80
1
I/O
O
ST
TTL
Digital I/O.
External memory address 17.
A17
RH2/A18
RH2
I/O
O
ST
TTL
Digital I/O.
External memory address 18.
A18
RH3/A19
RH3
2
I/O
O
ST
TTL
Digital I/O.
External memory address 19.
A19
RH4/AN12/P3C
RH4
22
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 12.
ECCP3 output P3C.
AN12
(7)
P3C
RH5/AN13/P3B
RH5
—
—
—
21
20
19
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 13.
ECCP3 output P3B.
AN13
(7)
P3B
RH6/AN14/P1C
RH6
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 14.
ECCP1 output P1C.
AN14
(7)
P1C
RH7/AN15/P1B
RH7
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 15.
ECCP1 output P1B.
AN15
(7)
P1B
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Input
= Power
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
O
= Output
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2005 Microchip Technology Inc.
DS39612B-page 19
MICROCHIP [ MICROCHIP ]
