PIC18F6525/6621/8525/8621
TABLE 1-2:
PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X
PIC18F8X2X
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
18
24
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6/C2OUT
RF1
17
16
23
18
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF1
15
14
13
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF1
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF1
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator VREF output.
AN10
CVREF
RF6/AN11
RF6
12
11
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS
RF7
I/O
I
ST
TTL
Digital I/O.
SPI™ slave select input.
SS
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Input
= Power
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
O
= Output
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2005 Microchip Technology Inc.
DS39612B-page 17
MICROCHIP [ MICROCHIP ]
