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PIC18F8621-I/PT 参数 Datasheet PDF下载

PIC18F8621-I/PT图片预览
型号: PIC18F8621-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能, 64 KB的增强型闪存微控制器与A / D [64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路装置时钟
文件页数/大小: 396 页 / 6639 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F6525/6621/8525/8621  
FIGURE 10-6:  
BLOCK DIAGRAM OF RB2:RB0 PINS  
VDD  
RBPU(2)  
Weak  
P
Pull-up  
Data Latch  
Data Bus  
D
Q
WR LATB or  
WR PORTB  
I/O pin(1)  
CK  
TRIS Latch  
D
Q
TTL  
Input  
Buffer  
WR TRISB  
CK  
RD TRISB  
Q
D
RD PORTB  
EN  
INTx  
RD Port  
Schmitt Trigger  
Buffer  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).  
FIGURE 10-7:  
BLOCK DIAGRAM OF RB3 PIN  
VDD  
Weak  
RBPU(2)  
CCP2MX  
P
Pull-up  
ECCP Output(3)  
1
VDD  
P
Enable(3)  
ECCP Output  
0
Data Latch  
Data Bus  
I/O pin(1)  
D
Q
WR LATB or  
WR PORTB  
N
CK  
VSS  
TRIS Latch  
D
TTL  
WR TRISB  
Input  
CK  
Q
Buffer  
RD TRISB  
RD LATB  
D
Q
RD PORTB  
EN  
RD PORTB  
ECCP2 or INT3  
Schmitt Trigger  
Buffer  
CCP2MX = 0  
Note 1: I/O pin has diode protection to VDD and VSS.  
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).  
3: For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0)  
in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or  
Extended Microcontroller mode.  
2005 Microchip Technology Inc.  
DS39612B-page 107  
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