PIC18F2331/2431/4331/4431
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
LVDCON
WDTCON
RCON
IDLEN
—
IRCF2
—
IRCF1
IRVST
—
IRCF0
LVDEN
—
OSTS
LVDL3
—
IOFS
LVDL2
—
SCS1
LVDL1
—
SCS0
LVDL0
SWDTEN
BOR
0000 q000
--00 0101
0--- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
00-0 0000
0000 0000
00-0 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
---- ---1
1111 1111
WDTW
IPEN
—
—
—
RI
TO
PD
POR
TMR1H
Timer1 Register High Byte
Timer1 Register Low Byte
TMR1L
T1CON
RD16
T1RUN
T1CKPS1
TOUTPS2
T1CKPS0
TOUTPS1
T1OSCEN
TOUTPS0
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
T2CKPS0
TMR2
Timer2 Register
PR2
Timer2 Period Register
TOUTPS3
T2CON
—
SSPBUF
SSPADD
SSPSTAT
SSPCON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
ADCON3
ADCHS
SSP Receive Buffer/Transmit Register
SSP Address Register in I2C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
SMP
CKE
D/A
P
S
R/W
UA
BF
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
ACONV
—
ACSCH
FIFOEN
ACQT1
SSRC4
GBSEL0
ACMOD1
BFEMT
ACQT0
SSRC3
GCSEL1
ACMOD0
BFOVFL
ADCS2
GO/DONE
ADPNT1
ADCS1
ADON
ADPNT0
ADCS0
SSRC0
GASEL0
VCFG1
ADFM
VCFG0
ACQT3
ADRS0
GDSEL0
ACQT2
—
ADRS1
GDSEL1
SSRC2
SSRC1
GBSEL1
GCSEL0
GASEL1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
ANSEL1
ANSEL0
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
—
—
ANS7(4)
—
—
ANS6(4)
DC2B1
—
ANS5(4)
DC2B0
—
CCP2M3
—
CCP2M2
—
CCP2M1
—
CCP2M0
ANS8(4)
ANS0
ANS4
ANS3
ANS2
ANS1
T5CON
QEICON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
T5SEN
VELM
RESEN(4)
T5MOD
T5PS1
QEIM2
T5PS0
QEIM1
T5SYNC
QEIM0
TMR5CS
PDEC1
TMR5ON
PDEC0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000X
-1-1 0-00
QERR
UP/DOWN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
CSRC
SPEN
—
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
RCSTA
BAUDCON
RCIDL
ABDEN
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.
2010 Microchip Technology Inc.
DS39616D-page 71
MICROCHIP [ MICROCHIP ]
