PIC18F2331/2431/4331/4431
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDC0L
PWM Duty Cycle #0L Register (lower 8 bits)
UNUSED PWM Duty Cycle #0H Register (upper 6 bits)
PWM Duty Cycle #1L Register (lower 8 bits)
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
---- 0000
-111 0000
0000 0-00
0000 0000
0000 0000
1111 1111
0000 0000
xxxx xxxx
PDC0H
PDC1L
PDC1H
UNUSED
PWM Duty Cycle #1H Register (upper 6 bits)
PDC2L
PWM Duty Cycle #2L Register (lower 8 bits)
PDC2H
UNUSED
PWM Duty Cycle #2H Register (upper 6 bits)
PDC3L(4)
PDC3H(4)
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
PWM Duty Cycle #3L Register (lower 8 bits)
UNUSED
PWM Duty Cycle #3H Register (upper 6 bits)
PWM Special Event Compare Register (lower 8 bits)
UNUSED
PWM Special Event Compare Register (upper 4 bits)
—
PWMEN2
SEVOPS2
DTPS0
PWMEN1
SEVOPS1
DT5
PWMEN0
SEVOPS0
DT4
PMOD3
SEVTDIR
DT3
PMOD2
—
PMOD1
UDIS
PMOD0
OSYNC
DT0
SEVOPS3
DTPS1
DT2
DT1
FLTCONFIG
OVDCOND
OVDCONS
BRFEN
FLTBS(4)
POVD6(4)
POUT6(4)
FLTBMOD(4)
FLTBEN(4)
FLTCON
POVD3
POUT3
FLTAS
POVD2
POUT2
FLTAMOD
POVD1
POUT1
FLTAEN
POVD0
POUT0
POVD7(4)
POUT7(4)
POVD5
POVD4
POUT5
POUT4
CAP1BUFH/
VELRH
Capture 1 Register High Byte/Velocity Register High Byte
CAP1BUFL/
VELRL
Capture 1 Register Low Byte/Velocity Register Low Byte
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
CAP2BUFH/
POSCNTH
Capture 2 Register High Byte/QEI Position Counter Register High Byte
Capture 2 Register Low Byte/QEI Position Counter Register Low Byte
Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte
Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte
CAP2BUFL/
POSCNTL
CAP3BUFH/
MAXCNTH
CAP3BUFL/
MAXCNTL
CAP1CON
CAP2CON
CAP3CON
DFLTCON
—
—
—
—
CAP1REN
CAP2REN
CAP3REN
FLT4EN
—
—
—
—
CAP1M3
CAP2M3
CAP3M3
FLT1EN
CAP1M2
CAP2M2
CAP3M2
FLTCK2
CAP1M1
CAP2M1
CAP3M1
FLTCK1
CAP1M0
CAP2M0
CAP3M0
FLTCK0
-0-- 0000
-0-- 0000
-0-- 0000
-000 0000
—
—
FLT3EN
FLT2EN
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.
2010 Microchip Technology Inc.
DS39616D-page 73
MICROCHIP [ MICROCHIP ]
