欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/P的Datasheet PDF文件第71页浏览型号PIC18F4431-I/P的Datasheet PDF文件第72页浏览型号PIC18F4431-I/P的Datasheet PDF文件第73页浏览型号PIC18F4431-I/P的Datasheet PDF文件第74页浏览型号PIC18F4431-I/P的Datasheet PDF文件第76页浏览型号PIC18F4431-I/P的Datasheet PDF文件第77页浏览型号PIC18F4431-I/P的Datasheet PDF文件第78页浏览型号PIC18F4431-I/P的Datasheet PDF文件第79页  
PIC18F2331/2431/4331/4431  
A few instructions, such as MOVFF, include the entire  
12-bit address (either source or destination) in their op  
6.7  
Data Addressing Modes  
The data memory space can be addressed in several  
ways. For most instructions, the addressing mode is  
fixed. Other instructions may use up to three modes,  
depending on which operands are used and whether or  
not the extended instruction set is enabled.  
codes. In these cases, the BSR is ignored entirely.  
The destination of the operation’s results is determined  
by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are  
stored back in the source register, overwriting its origi-  
nal contents. When ‘d’ is ‘0’, the results are stored in  
the W register. Instructions without the ‘d’ argument  
have a destination that is implicit in the instruction; their  
destination is either the target register being operated  
on or the W register.  
The addressing modes are:  
• Inherent  
• Literal  
• Direct  
• Indirect  
6.7.3  
INDIRECT ADDRESSING  
Indirect Addressing allows the user to access a location  
in data memory without giving a fixed address in the  
instruction. This is done by using File Select Registers  
(FSRs) as pointers to the locations to be read or written  
to. Since the FSRs are themselves located in RAM as  
Special Function Registers, they can also be directly  
manipulated under program control. This makes FSRs  
very useful in implementing data structures, such as  
tables and arrays in data memory.  
6.7.1  
INHERENT AND LITERAL  
ADDRESSING  
Many PIC18 control instructions do not need any  
argument at all. They either perform an operation that  
globally affects the device or they operate implicitly on  
one register. This addressing mode is known as Inherent  
Addressing. Examples include SLEEP, RESETand DAW.  
Other instructions work in a similar way but require an  
additional explicit argument in the opcode. This is  
known as Literal Addressing mode because they  
require some literal value as an argument. Examples  
include ADDLWand MOVLW, which respectively, add or  
move a literal value to the W register. Other examples  
include CALL and GOTO, which include a 20-bit  
program memory address.  
The registers for Indirect Addressing are also  
implemented with Indirect File Operands (INDFs) that  
permit automatic manipulation of the pointer value with  
auto-incrementing, auto-decrementing or offsetting  
with another value. This allows for efficient code, using  
loops, such as the example of clearing an entire RAM  
bank in Example 6-5.  
6.7.2  
DIRECT ADDRESSING  
EXAMPLE 6-5:  
HOW TO CLEAR RAM  
(BANK 1) USING  
INDIRECT ADDRESSING  
Direct Addressing specifies all or part of the source  
and/or destination address of the operation within the  
opcode itself. The options are specified by the  
arguments accompanying the instruction.  
LFSR  
FSR0, 100h ;  
NEXT  
CLRF  
POSTINC0  
; Clear INDF  
In the core PIC18 instruction set, bit-oriented and byte-  
oriented instructions use some version of Direct  
Addressing by default. All of these instructions include  
some 8-bit literal address as their Least Significant  
Byte. This address specifies either a register address in  
one of the banks of data RAM (Section 6.5.4 “Special  
Function Registers”) or a location in the Access Bank  
(Section 6.5.2 “Access Bank”) as the data source for  
the instruction.  
; register then  
; inc pointer  
; All done with  
; Bank1?  
; NO, clear next  
; YES, continue  
BTFSS FSR0H, 1  
BRA NEXT  
CONTINUE  
The Access RAM bit, ‘a’, determines how the address  
is interpreted. When ‘a’ is ‘1’, the contents of the BSR  
(Section 6.5.1 “Bank Select Register (BSR)”) are  
used with the address to determine the complete 12-bit  
address of the register. When ‘a’ is ‘0’, the address is  
interpreted as being a register in the Access Bank.  
Addressing that uses the Access RAM is sometimes  
also known as Direct Forced Addressing mode.  
2010 Microchip Technology Inc.  
DS39616D-page 75