PIC18F2331/2431/4331/4431
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(3)
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21(3)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
xxxx xxxx
---- 0000
N/A
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
TMR0L
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
T0CON
TMR0ON
T016BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.
DS39616D-page 70
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
