PIC18F2331/2431/4331/4431
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEADR
EEDATA
EECON2
EECON1
IPR3
EEPROM Address Register
EEPROM Data Register
0000 0000
0000 0000
0000 0000
xx-0 x000
---1 1111
---0 0000
---0 0000
1--1 -1-1
0--0 -0-0
0--0 -0-0
-111 1111
-000 0000
-000 0000
--00 0000
00-0 0000
0000 0000
---- -111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
0000 0000
00-- ----
0000 0000
---- 0000
1111 1111
---- 1111
EEPROM Control Register 2 (not a physical register)
EEPGD
—
CFGS
—
—
—
FREE
PTIP
PTIF
WRERR
IC3DRIP
IC3DRIF
IC3DRIE
—
WREN
IC2QEIP
IC2QEIF
IC2QEIE
LVDIP
WR
IC1IP
IC1IF
IC1IE
—
RD
TMR5IP
TMR5IF
TMR5IE
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
PIR3
—
—
—
PIE3
—
—
—
PTIE
EEIP
EEIF
EEIE
TXIP
TXIF
IPR2
OSCFIP
OSCFIF
OSCFIE
—
—
—
PIR2
—
—
—
LVDIF
—
PIE2
—
—
—
LVDIE
—
IPR1
ADIP
ADIF
ADIE
—
RCIP
RCIF
RCIE
TUN5
—
SSPIP
SSPIF
SSPIE
TUN3
SSRC3
GCSEL1
—
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR2IP
TMR2IF
TMR2IE
TUN1
SSRC1
GASEL1
PIR1
—
PIE1
—
TXIE
TUN4
SSRC4
GBSEL0
—
OSCTUNE
ADCON3
ADCHS
TRISE(4)
TRISD(4)
TRISC
TRISB
TRISA
PR5H
—
ADRS1
GDSEL1
—
ADRS0
GDSEL0
—
SSRC2
GCSEL0
PORTE Data Direction Register(4)
SSRC0
GASEL0
GBSEL1
—
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
TRISA7(2)
TRISA6(1) PORTA Data Direction Register
Timer5 Period Register High Byte
Timer5 Period Register Low Byte
PR5L
LATE(4)
LATD(4)
LATC
—
—
—
—
—
LATE Data Output Register
LATD Data Output Register
LATC Data Output Register
LATB Data Output Register
LATB
LATA
LATA7(2)
LATA6(1)
LATA Data Output Register
TMR5H
TMR5L
PORTE
PORTD(4)
PORTC
PORTB
PORTA
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
Timer5 Register High Byte
Timer5 Register Low Byte
—
RD7
—
RD6
—
RD5
RC5
RB5
—
RD4
RC4
RB4
RE3(4,5)
RD3
RE2(4)
RD2
RE1(4)
RD1
RE0(4)
RD0
RC7
RC6
RC3
RC2
RC1
RC0
RB7
RB6
RB3
RB2
RB1
RB0
RA7(2)
PTOPS3
PTEN
RA6(1)
PTOPS2
PTDIR
RA5
RA4
RA3
RA2
RA1
RA0
PTOPS1
—
PTOPS0
—
PTCKPS1
—
PTCKPS0
—
PTMOD1
—
PTMOD0
—
PWM Time Base Register (lower 8 bits)
UNUSED
PWM Time Base Register (upper 4 bits)
PWM Time Base Period Register (lower 8 bits)
UNUSED
PWM Time Base Period Register (upper 4 bits)
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.
DS39616D-page 72
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
