PIC18F2331/2431/4331/4431
TABLE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
—
s
ms
31
Watchdog Timer Time-out Period
(no postscaler)
—
4.00
32
33
TOST
Oscillation Start-up Timer Period
1024 TOSC
—
—
1024 TOSC
—
TOSC = OSC1 period
TPWRT Power-up Timer Period
65.5
ms
—
—
34
TIOZ
I/O High-impedance from MCLR
—
2
s
Low or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
s VDD BVDD (see D005)
s
TIRVST Time for Internal Reference
Voltage to become Stable
20
50
37
38
39
TLVD
TCSD
Low-Voltage Detect Pulse Width
CPU Start-up Time
200
—
—
10
1
—
—
—
s
s
ms
VDD VLVD
TIOBST Time for INTOSC to Stabilize
—
DS39616D-page 350
2010 Microchip Technology Inc.