PIC18F2331/2431/4331/4431
26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 26-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
DC
DC
0.1
4
40
4
MHz EC, ECIO
MHz RC osc
MHz XT osc
MHz HS osc
4
25
4
10
MHz HS + PLL osc
kHz LP Osc mode
5
200
—
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
25
250
250
ns
ns
ns
EC, ECIO
RC osc
XT osc
—
10,000
25
100
250
250
ns
ns
HS osc
HS + PLL osc
25
100
30
2.5
10
—
—
—
s
ns
ns
s
ns
ns
ns
ns
LP osc
2
3
TCY
Instruction Cycle Time(1)
TCY = 4/FOSC
XT osc
TosL,
TosH
External Clock in (OSC1)
High or Low Time
—
—
LP osc
—
HS osc
XT osc
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
LP osc
—
HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39616D-page 346
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
