PIC18F2331/2431/4331/4431
18.11.3 PWM OUTPUT PIN RESET STATES
18.12.1 FAULT PIN ENABLE BITS
The PWMPIN Configuration bit determines the PWM
output pins to be PWM output pins or digital I/O pins,
after the device comes out of Reset. If the PWMPIN
Configuration bit is unprogrammed (default), the
PWMEN<2:0> control bits will be cleared on a device
Reset. Consequently, all PWM outputs will be tri-stated
and controlled by the corresponding PORT and TRIS
registers. If the PWMPIN Configuration bit is pro-
grammed low, the PWMEN<2:0> control bits will be
set, as follows, on a device Reset:
By setting the bits, FLTAEN and FLTBEN in the
FLTCONFIG register, the corresponding Fault inputs
are enabled. If both bits are cleared, then the Fault
inputs have no effect on the PWM module.
18.12.2 MFAULT INPUT MODES
The FLTAMOD and FLTBMOD bits in the FLTCONFIG
register determine the modes of PWM I/O pins that are
deactivated when they are overridden by Fault input.
The FLTAS and FLTBS bits in the FLTCONFIG register
give the status of Fault A and Fault B inputs.
• PWMEN<2:0> = 101if device has 8 PWM pins
(PIC18F4331/4431 devices)
Each of the Fault inputs have two modes of operation:
• PWMEN<2:0> = 100if device has 6 PWM pins
(PIC18F2331/2431 devices)
• Inactive Mode (FLTxMOD = 0)
This is a Catastrophic Fault Management mode.
When the Fault occurs in this mode, the PWM out-
puts are deactivated. The PWM pins will remain in
Inactivate mode until the Fault is cleared (Fault
input is driven high) and the corresponding Fault
Status bit has been cleared in software. The PWM
outputs are enabled immediately at the beginning
of the following PWM period, after the Fault Status
bit (FLTxS) is cleared.
All PWM pins will be enabled for PWM output and will
have the output polarity defined by the HPOL and
LPOL Configuration bits.
18.12 PWM Fault Inputs
There are two Fault inputs associated with the PWM
module. The main purpose of the input Fault pins is to
disable the PWM output signals and drive them into an
inactive state. The action of the Fault inputs is
performed directly in hardware so that when a Fault
occurs, it can be managed quickly and the PWM
outputs are put into an inactive state to save the power
devices connected to the PWMs.
• Cycle-by-Cycle Mode (FLTxMOD = 1)
When the Fault occurs in this mode, the PWM
outputs are deactivated. The PWM outputs will
remain in the defined Fault states (all PWM
outputs inactive) for as long as the Fault pin is held
low. After the Fault pin is driven high, the PWM
outputs will return to normal operation at the begin-
ning of the following PWM period and the FLTxS
bit is automatically cleared.
The PWM Fault inputs are FLTA and FLTB, which can
come from I/O pins, the CPU or another module. The
FLTA and FLTB pins are active-low inputs so it is easy to
“OR” many sources to the same input. FLTB and its asso-
ciated logic are not implemented on PIC18F2331/2431
devices.
The FLTCONFIG register (Register 18-8) defines the
settings of FLTA and FLTB inputs.
Note:
The inactive state of the PWM pins are
dependent on the HPOL and LPOL Con-
figuration bit settings, which define the
active and inactive state for PWM outputs.
2010 Microchip Technology Inc.
DS39616D-page 199
MICROCHIP [ MICROCHIP ]
